Device Usage Page (usage_statistics_webtalk.html)

This HTML page displays the device usage statistics that will be sent to Xilinx.
To see the actual file transmitted to Xilinx, please click here.

software_version_and_target_device
betaFALSE build_version2552052
date_generatedTue Jan 16 10:04:54 2024 os_platformWIN64
product_versionVivado v2019.1 (64-bit) project_id3ab26b1971e74264a71e7f95200a4848
project_iteration1 random_ideb578f207f0a508887bec95b6a90a5c0
registration_id174120818_174120819_0_149 route_designTRUE
target_devicexc7a35ti target_familyartix7
target_packagecpg236 target_speed-1L
tool_flowVivado

user_environment
cpu_nameIntel(R) Core(TM) i7-10700 CPU @ 2.90GHz cpu_speed2904 MHz
os_nameWindows Server 2016 or Windows 10 os_releasemajor release (build 9200)
system_ram34.000 GB total_processors1

vivado_usage
gui_handlers
abstractcombinedpanel_add_element=1 addsrcwizard_specify_hdl_netlist_block_design=1 addsrcwizard_specify_or_create_constraint_files=1 basedialog_cancel=2
basedialog_no=1 basedialog_ok=16 basedialog_yes=5 constraintschooserpanel_add_files=1
createsrcfiledialog_file_name=1 definemodulesdialog_define_modules_and_specify_io_ports=13 filesetpanel_file_set_panel_tree=13 flownavigatortreepanel_flow_navigator_tree=6
fpgachooser_family=2 fpgachooser_fpga_table=2 fpgachooser_package=2 gettingstartedview_create_new_project=1
hcodeeditor_search_text_combo_box=1 mainmenumgr_checkpoint=2 mainmenumgr_export=1 mainmenumgr_file=4
mainmenumgr_ip=2 mainmenumgr_project=2 mainmenumgr_text_editor=3 msgtreepanel_message_view_tree=1
msgview_warning_messages=2 pacommandnames_add_sources=5 pacommandnames_new_file=1 pacommandnames_open_file=1
pacommandnames_run_bitgen=1 paviews_code=2 projectnamechooser_choose_project_location=1 projectnamechooser_project_name=1
rdicommands_line_comment=3 rdicommands_save_file=8 settingsprojectgeneralpage_choose_device_for_your_project=1 srcchooserpanel_add_hdl_and_netlist_files_to_your_project=2
srcchooserpanel_create_file=1 srcchooserpanel_make_local_copy_of_these_files_into=1 statemonitor_reset_run=1 syntheticastatemonitor_cancel=1
java_command_handlers
addsources=5 editdelete=1 editundo=1 newfile=1
newproject=1 openfile=1 runbitgen=1 runimplementation=5
showview=3 toolssettings=1
other_data
guimode=1
project_data
constraintsetcount=1 core_container=false currentimplrun=impl_1 currentsynthesisrun=synth_1
default_library=xil_defaultlib designmode=RTL export_simulation_activehdl=0 export_simulation_ies=0
export_simulation_modelsim=0 export_simulation_questa=0 export_simulation_riviera=0 export_simulation_vcs=0
export_simulation_xsim=0 implstrategy=Vivado Implementation Defaults launch_simulation_activehdl=0 launch_simulation_ies=0
launch_simulation_modelsim=0 launch_simulation_questa=0 launch_simulation_riviera=0 launch_simulation_vcs=0
launch_simulation_xsim=0 simulator_language=Mixed srcsetcount=3 synthesisstrategy=Vivado Synthesis Defaults
target_language=VHDL target_simulator=XSim totalimplruns=1 totalsynthesisruns=1

unisim_transformation
post_unisim_transformation
ibuf=16 obuf=16
pre_unisim_transformation
ibuf=16 obuf=16

report_drc
command_line_options
-append=default::[not_specified] -checks=default::[not_specified] -fail_on=default::[not_specified] -force=default::[not_specified]
-format=default::[not_specified] -internal=default::[not_specified] -internal_only=default::[not_specified] -messages=default::[not_specified]
-name=default::[not_specified] -no_waivers=default::[not_specified] -return_string=default::[not_specified] -ruledecks=default::[not_specified]
-upgrade_cw=default::[not_specified] -waived=default::[not_specified]
results
cfgbvs-1=1

report_utilization
clocking
bufgctrl_available=32 bufgctrl_fixed=0 bufgctrl_used=0 bufgctrl_util_percentage=0.00
bufhce_available=72 bufhce_fixed=0 bufhce_used=0 bufhce_util_percentage=0.00
bufio_available=20 bufio_fixed=0 bufio_used=0 bufio_util_percentage=0.00
bufmrce_available=10 bufmrce_fixed=0 bufmrce_used=0 bufmrce_util_percentage=0.00
bufr_available=20 bufr_fixed=0 bufr_used=0 bufr_util_percentage=0.00
mmcme2_adv_available=5 mmcme2_adv_fixed=0 mmcme2_adv_used=0 mmcme2_adv_util_percentage=0.00
plle2_adv_available=5 plle2_adv_fixed=0 plle2_adv_used=0 plle2_adv_util_percentage=0.00
dsp
dsps_available=90 dsps_fixed=0 dsps_used=0 dsps_util_percentage=0.00
io_standard
blvds_25=0 diff_hstl_i=0 diff_hstl_i_18=0 diff_hstl_ii=0
diff_hstl_ii_18=0 diff_hsul_12=0 diff_mobile_ddr=0 diff_sstl135=0
diff_sstl135_r=0 diff_sstl15=0 diff_sstl15_r=0 diff_sstl18_i=0
diff_sstl18_ii=0 hstl_i=0 hstl_i_18=0 hstl_ii=0
hstl_ii_18=0 hsul_12=0 lvcmos12=0 lvcmos15=0
lvcmos18=0 lvcmos25=0 lvcmos33=1 lvds_25=0
lvttl=0 mini_lvds_25=0 mobile_ddr=0 pci33_3=0
ppds_25=0 rsds_25=0 sstl135=0 sstl135_r=0
sstl15=0 sstl15_r=0 sstl18_i=0 sstl18_ii=0
tmds_33=0
memory
block_ram_tile_available=50 block_ram_tile_fixed=0 block_ram_tile_used=0 block_ram_tile_util_percentage=0.00
ramb18_available=100 ramb18_fixed=0 ramb18_used=0 ramb18_util_percentage=0.00
ramb36_fifo_available=50 ramb36_fifo_fixed=0 ramb36_fifo_used=0 ramb36_fifo_util_percentage=0.00
primitives
ibuf_functional_category=IO ibuf_used=16 obuf_functional_category=IO obuf_used=16
slice_logic
f7_muxes_available=16300 f7_muxes_fixed=0 f7_muxes_used=0 f7_muxes_util_percentage=0.00
f8_muxes_available=8150 f8_muxes_fixed=0 f8_muxes_used=0 f8_muxes_util_percentage=0.00
lut_as_logic_available=20800 lut_as_logic_fixed=0 lut_as_logic_used=0 lut_as_logic_util_percentage=0.00
lut_as_memory_available=9600 lut_as_memory_fixed=0 lut_as_memory_used=0 lut_as_memory_util_percentage=0.00
register_as_flip_flop_available=41600 register_as_flip_flop_fixed=0 register_as_flip_flop_used=0 register_as_flip_flop_util_percentage=0.00
register_as_latch_available=41600 register_as_latch_fixed=0 register_as_latch_used=0 register_as_latch_util_percentage=0.00
slice_luts_available=20800 slice_luts_fixed=0 slice_luts_used=0 slice_luts_util_percentage=0.00
slice_registers_available=41600 slice_registers_fixed=0 slice_registers_used=0 slice_registers_util_percentage=0.00
lut_as_distributed_ram_fixed=0 lut_as_distributed_ram_used=0 lut_as_logic_available=20800 lut_as_logic_fixed=0
lut_as_logic_used=0 lut_as_logic_util_percentage=0.00 lut_as_memory_available=9600 lut_as_memory_fixed=0
lut_as_memory_used=0 lut_as_memory_util_percentage=0.00 lut_as_shift_register_fixed=0 lut_as_shift_register_used=0
register_driven_from_outside_the_slice_fixed=0 register_driven_from_outside_the_slice_used=0 register_driven_from_within_the_slice_fixed=0 register_driven_from_within_the_slice_used=0
slice_available=8150 slice_fixed=0 slice_registers_available=41600 slice_registers_fixed=0
slice_registers_used=0 slice_registers_util_percentage=0.00 slice_used=0 slice_util_percentage=0.00
slicel_fixed=0 slicel_used=0 slicem_fixed=0 slicem_used=0
unique_control_sets_available=8150 unique_control_sets_fixed=8150 unique_control_sets_used=0 unique_control_sets_util_percentage=0.00
specific_feature
bscane2_available=4 bscane2_fixed=0 bscane2_used=0 bscane2_util_percentage=0.00
capturee2_available=1 capturee2_fixed=0 capturee2_used=0 capturee2_util_percentage=0.00
dna_port_available=1 dna_port_fixed=0 dna_port_used=0 dna_port_util_percentage=0.00
efuse_usr_available=1 efuse_usr_fixed=0 efuse_usr_used=0 efuse_usr_util_percentage=0.00
frame_ecce2_available=1 frame_ecce2_fixed=0 frame_ecce2_used=0 frame_ecce2_util_percentage=0.00
icape2_available=2 icape2_fixed=0 icape2_used=0 icape2_util_percentage=0.00
pcie_2_1_available=1 pcie_2_1_fixed=0 pcie_2_1_used=0 pcie_2_1_util_percentage=0.00
startupe2_available=1 startupe2_fixed=0 startupe2_used=0 startupe2_util_percentage=0.00
xadc_available=1 xadc_fixed=0 xadc_used=0 xadc_util_percentage=0.00

synthesis
command_line_options
-assert=default::[not_specified] -bufg=default::12 -cascade_dsp=default::auto -constrset=default::[not_specified]
-control_set_opt_threshold=default::auto -directive=default::default -fanout_limit=default::10000 -flatten_hierarchy=default::rebuilt
-fsm_extraction=default::auto -gated_clock_conversion=default::off -generic=default::[not_specified] -include_dirs=default::[not_specified]
-keep_equivalent_registers=default::[not_specified] -max_bram=default::-1 -max_bram_cascade_height=default::-1 -max_dsp=default::-1
-max_uram=default::-1 -max_uram_cascade_height=default::-1 -mode=default::default -name=default::[not_specified]
-no_lc=default::[not_specified] -no_srlextract=default::[not_specified] -no_timing_driven=default::[not_specified] -part=xc7a35ticpg236-1L
-resource_sharing=default::auto -retiming=default::[not_specified] -rtl=default::[not_specified] -rtl_skip_constraints=default::[not_specified]
-rtl_skip_ip=default::[not_specified] -seu_protect=default::none -sfcu=default::[not_specified] -shreg_min_size=default::3
-top=main -verilog_define=default::[not_specified]
usage
elapsed=00:00:20s hls_ip=0 memory_gain=563.930MB memory_peak=863.137MB